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| Features * Ultra High Performance - System Speeds to 100 MHz - Array Multipliers > 50 MHz - 10 ns Flexible SRAM - Internal Tri-state Capability in Each Cell FreeRAMTM - Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM - 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells 128 - 384 PCI Compliant I/Os - 3V/5V Capability - Programmable Output Drive - Fast, Flexible Array Access Facilitates Pin Locking - Pin-compatible with XC4000, XC5200 FPGAs 8 Global Clocks - Fast, Low Skew Clock Distribution - Programmable Rising/Falling Edge Transitions - Distributed Clock Shutdown Capability for Low Power Management - Global Reset/Asynchronous Reset Options - 4 Additional Dedicated PCI Clocks Cache Logic(R) Dynamic Full/Partial Re-configurability In-System - Unlimited Re-programmability via Serial or Parallel Modes - Enables Adaptive Designs - Enables Fast Vector Multiplier Updates - QuickChangeTM Tools for Fast, Easy Design Changes Pin-compatible Package Options - Plastic Leaded Chip Carriers (PLCC) - Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP) - Ball Grid Arrays (BGAs) Industry-standard Design Tools - Seamless Integration (Libraries, Interface, Full Back-annotation) with Concept(R), Everest, ExemplarTM, Mentor(R), OrCAD(R), SynarioTM, Synopsys(R), Verilog(R), Veribest(R), Viewlogic(R), Synplicity(R) - Timing Driven Placement & Routing - Automatic/Interactive Multi-chip Partitioning - Fast, Efficient Synthesis - Over 75 Automatic Component Generators Create 1000s of Reusable, Fully Deterministic Logic and RAM Functions Intellectual Property Cores - Fir Filters, UARTs, PCI, FFT and Other System Level Functions Easy Migration to Atmel Gate Arrays for High Volume Production Supply Voltage 5V for AT40K, and 3.3V for AT40KLV * * * 5K - 50K Gates Coprocessor FPGA with FreeRAMTM AT40K05 AT40K05LV AT40K10 AT40K10LV AT40K20 AT40K20LV AT40K40 AT40K40LV * * * * * * Rev. 0896C-FPGA-04/02 1 Table 1. AT40K/AT40KLV Family(1) Device Usable Gates Rows x Columns Cells Registers RAM Bits I/O (Maximum) Note: AT40K05 AT40K05LV 5K - 10K 16 x 16 256 256(1) 2,048 128 AT40K10 AT40K10LV 10K - 20K 24 x 24 576 576(1) 4,608 192 AT40K20 AT40K20LV 20K - 30K 32 x 32 1,024 1,024(1) 8,192 256 AT40K40 AT40K40LV 40K - 50K 48 x 48 2,304 2,304(1) 18,432 384 1. Packages with FCK will have 8 less registers. Description The AT40K/AT40KLV is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for AT40KLV. The AT40K/AT40KLV is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform. Atmel's design tools provide seamless integration with industry standard tools such as Synplicity, ModelSim, Exemplar and Viewlogic. The AT40K/AT40KLV can be used as a coprocessor for high-speed (DSP/processorbased) designs by implementing a variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications. Fast, Flexible and Efficient SRAM The AT40K/AT40KLV FPGA offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool. The AT40K/AT40KLV's patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40K/AT40KLV's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. Fast, Efficient Array and Vector Multipliers 2 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Cache Logic Design The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40K/AT40KLV can act as a reconfigurable coprocessor. The AT40K/AT40KLV FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators work seamlessly with industry standard schematic and synthesis tools to create the fastest, most efficient designs available. The patented AT40K/AT40KLV series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to 2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for easy design migration in the same package footprint. The AT40K/AT40KLV series FPGAs utilize a reliable 0.6 single-poly, CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based integrated development system (IDS) is used to create AT40K/AT40KLV series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell's small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. Automatic Component Generators 3 0896C-FPGA-04/02 The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells, see Figure 1. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells, see Figure 2 on page 5. At the intersection of each repeater row and column there is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM(1), with either synchronous or asynchronous operation. Note: 1. The right-most column can only be used as single-port RAM. Figure 1. Symmetrical Array Surrounded by I/O (AT40K20) = I/O Pad = AT40K Cell = Repeater Row = Repeater Column = FreeRAM 4 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 2. Floor Plan (Representative Portion)(1) RV = Vertical Repeater = Horizontal Repeater = Core Cell RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM Note: 1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool. 5 0896C-FPGA-04/02 The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-bus segment spans eight cells and "leapfrogs" or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are implemented through pass gates in the cell-bus interface. Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resources on the AT40K/AT40KLV are used as a dual-function resources. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40K/AT40KLV software tools are designed to accommodate dualfunction buses in an efficient manner. Table 2. Dual-function Buses Function Cell Output Enable RAM Output Enable Type Local Express Plane(s) 5 2 Direction Horizontal and Vertical Vertical Bus full length at array edge Bus in first column to left of RAM block Bus full length at array edge Bus in first column to left of RAM block Buses full length at array edge Buses in second column to left of RAM block Data In connects to local bus plane 1 Data out connects to local bus plane 2 Bus half length at array edge Bus half length at array edge Comments RAM Write Enable Express 1 Vertical RAM Address Express 1-5 Vertical RAM Data In RAM Data Out Clocking Set/Reset Local Local Express Express 1 2 4 5 Horizontal Horizontal Vertical Vertical 6 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 3. Busing Plane (One of Five) = AT40K/AT40KLV Core Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater Express Express Bus Bus Local Bus 7 0896C-FPGA-04/02 Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). Figure 4. Cell Connections CELL CELL CELL Plane 5 Plane 4 Plane 3 Plane 2 Plane 1 CELL CELL CELL Plane 5 Plane 4 Plane 3 Plane 2 Plane 1 Horizontal Busing Plane WXYZL W X Y Z L CELL Vertical Busing Plane Diagonal Direct Connect CELL CELL Orthogonal Direct Connect CELL (a) Cell-to-cell Connections (b) Cell-to-bus Connections The Cell Figure 5 depicts the AT40K/AT40KLV cell. Configuration bits for separate muxes and pass gates are independent. All permutations of programmable muxes and pass gates are legal. Vn (V1 - V 5) is connected to the vertical local bus in plane n. H n (H 1 - H5) is connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let signals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. This allows bus signals to switch planes to achieve greater route ability. Up to five simultaneous local/local turns are possible. The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tristated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the "front end" of the cell. This AND gate is an important feature in the implementation of efficient array multipliers. With this functionality in each core cell, the core cell can be configured in several "modes". The core cell flexibility makes the AT40K/AT40KLV architecture well suited to most digital design application areas, see Figure 6. 8 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 5. The Cell "1" NW NE SE SW "1" "1" N E S W X W Y Z FB X W Y 8X1 LUT 8X1 LUT OUT "0" "1" OUT "1" V1 H1 V2 H2 V3 H3 V4 H4 V5 H5 10 Z D Q CLOCK RESET/SET "1" OEH OEV L Pass gates X Y NW NE SE SW N E S W X Y W Z FB = = = = = Diagonal Direct Connect or Bus Orthogonal Direct Connect or Bus Bus Connection Bus Connection Internal Feedback 9 0896C-FPGA-04/02 Figure 6. Some Single Cell Modes A B C D Synthesis Mode. This mode is particularly important for the use of VHDL/Verilog design. VHDL/Verilog Synthesis tools generally will produce as their output large amounts of random logic functions. Having a 4-input LUT structure gives efficient random logic optimization without the delays associated with larger LUT structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell. Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40K/AT40KLV core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell. LUT DQ Q (Registered) and/or Q SUM LUT or DQ A B C LUT SUM (Registered) and/or CARRY LUT DSP/Multiplier Mode. This mode is used to efficiently DQ A B C D PRODUCT (Registered) implement array multipliers. An array multiplier is an array or of bitwise multipliers, each implemented as a full adder PRODUCT and/or LUT CARRY with an upstream AND gate. Using this AND gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the AT40K/AT40KLV architecture. DQ Q and/or CARRY IN LUT Counter Mode. Counters are fundamental to almost all digital designs. They are the basis of state machines, timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit counter can be implemented in one core cell. Again, the output can be registered, tri-stated and/or fed back. LUT CARRY A B C EN Q Tri-state/Mux Mode. This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching. 10 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 2:1 MUX AT40K/AT40KLV Series FPGA RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sectors in the same column. A 5-bit Output Address Bus connects to five vertical express buses in the same column. Ain (input address) and Aout (output address) alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to the vertical express buses in the same column. Figure 7. RAM Connections (One Ram Block) CLK CLK CLK CLK Din Ain Dout Aout 32 x 4 RAM CLK WEN OEN 11 0896C-FPGA-04/02 Reading and writing of the 10 ns 32 x 4 dual-port FreeRAM are independent of each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load is logic 0, data is latched. These latches are used to synchronize Write Address, Write Enable Not, and Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0, data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous RAM) or they both select "1" (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the "AT40K Configuration Series" application note at www.atmel.com). Figure 8. RAM Logic CLOCK "1" 0 1 1 "1" 0 Ain 5 Load Read Address Aout 5 Load Latch Write Address WEN Load 32 x 4 Dual-port RAM Write Enable NOT "1" OE Latch Din 4 Load 4 Din Clear Latch Dout Dout RAM-Clear Byte Figure 9 on page 13 shows an example of a RAM macro constructed using the AT40K/AT40KLV's FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators. 12 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 0896C-FPGA-04/02 Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) WE Write Address 2-to-4 Decoder 2-to-4 Decoder Read Address Dout(0) Dout(1) Dout(2) Dout(3) AT40K/AT40KLV Series FPGA Din(0) Din(1) Din(2) Din(3) Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din(4) Din(5) Din(6) Din(7) Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Dout(4) Dout(5) Dout(6) Dout(7) Local Buses Express Buses Dedicated Connections 13 Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per edge column of the array for PCI specification. Each column of an array has a "Column Clock mux" and a "Sector Clock mux". The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to "0", using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus, see Figure 10 on page 15. The extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to provide fast clocking to right-side I/Os. The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant "0" is provided to each register's clock pins. After configuration on power-up, the registers either set or reset, depending on the user's choice. The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array. 14 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 10. Clocking (for One Column of Cells) } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux "1" Sector Clock Mux Global Clock Line (Buried) Express Bus (Plane 4; Half Length at Edge) "1" Repeater Sector Clock Mux "1" "1" 15 0896C-FPGA-04/02 Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network. The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux, see Figure 11 on page 17. The set/reset provided to each sector column of four cells is either inverted or non-inverted using the Sector Reset mux. The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up). 16 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 11. Set/Reset (for One Column of Cells) Each Cell has a Programmable Set or Reset Sector Set/Reset Mux Repeater "1" Global Set/Reset Line (Buried) "1" Express Bus (Plane 5; Half Length at Edge) "1" "1" Any User I/O can Drive Global Set/Reset Lone 17 0896C-FPGA-04/02 I/O Structure PAD The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the device size and package. These unbonded I/Os are used to perform a variety of bus turns at the edge of the array. Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak "1" or "0" level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin. The input stage of each I/O cell has a number of parameters that can be programmed either as properties in schematic entry or in the I/O Pad Attributes editor in IDS. TTL/CMOS SCHMITT The threshold level can be set to either TTL/CMOS-compatible levels. A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative comparator circuit that adds 1V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. The input buffer can be programmed to include four different intrinsic delays as specified in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal. The output drive capabilities of each I/O are programmable. They can be set to FAST, MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability (20 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive (14 mA at 5V) buffer, while SLOW yields a standard (6 mA at 5V) buffer. The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open drain (0 or Z) by programming an I/O's Source Selection mux. Of course, the output can be normal (0 or 1), as well. The Source Selection mux selects the source for the output signal of an I/O, see Figure 12 on page 20. PULL-UP/PULL-DOWN DELAYS DRIVE TRI-STATE SOURCE SELECTION MUX 18 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Primary, Secondary and Corner I/Os Primary I/O The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Primary I/O and two Secondary I/Os. Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It also connects into the repeaters on the row immediately above and below the adjacent core cell. In addition, each Primary I/O also connects into the busing network of the three nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Primary I/O can be accessed from any logic cell on three separate rows or columns of the FPGA. See Figures 12a on page 20 and 13a on page 21. Every logic cell at the edge of the FPGA array has two direct diagonal connections to a Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O connects on the diagonal inputs to the cell above and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of the two nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Secondary I/O can be accessed from any logic cell on two rows or columns of the FPGA. See Figure 12b on page 20 and Figure 13b. Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40K/AT40KLV FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array. This means that many different edge logic cells can access the Corner I/Os. See Figure 14 on page 22. Secondary I/O Corner I/O 19 0896C-FPGA-04/02 Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV TRI-STATE CELL "0" "1" VCC DRIVE PULL-UP "0" PAD "1" CELL PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT DELAY GND CELL (a) Primary I/O TRI-STATE "0" "1" CELL VCC DRIVE PULL-UP "0" "1" PAD PULL-DOWN TTL/CMOS SCHMITT DELAY SOURCE DELAY SELECT MUX GND CELL (b) Secondary I/O 20 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV TRI-STATE CELL "0" "1" VCC DRIVE PULL-UP "0" PAD "1" CELL PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY (a) Primary I/O CELL TRI-STATE "0" "1" CELL VCC DRIVE PULL-UP "0" "1" PAD PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY CELL (a) Secondary I/O 21 0896C-FPGA-04/02 Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV PULL-DOWN PULL-DOWN GND TTL/CMOS SCHMITT DELAY PULL-UP PULL-UP PAD PAD VCC DRIVE TRI-STATE GND TTL/CMOS SCHMITT TRI-STATE DELAY VCC DRIVE "0" "1" "0" "1" "0" "1" "0" TRI-STATE "0" "1" VCC DRIVE PULL-UP "0" PAD "1" CELL CELL PULL-DOWN TTL/CMOS SCHMITT DELAY GND "1" CELL 22 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Absolute Maximum Ratings - 5V Commercial/Industrial* AT40K Operating Temperature.................................. -55C to +125 C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground .................................-0.5V to V CC +7V Supply Voltage (VCC ) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 250C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. DC and AC Operating Range - 5V Operation AT40K Commercial -2 Operating Temperature (Case) VCC Power Supply Input Voltage Level (TTL) High (VIHT) Low (VILT) Input Voltage Level (CMOS) High (VIHC) Low (VILC) 0C - 70C 5V 5% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC Industrial -2 -40C - 85C 5V 10% 2.0V - V CC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC Military -2 -55C - 125C 5V 10% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC 23 0896C-FPGA-04/02 DC Characteristics - 5V Operation Commercial/Industrial/Military AT40K Symbol VIH Parameter High-level Input Voltage TTL CMOS VIL Low-level Input Voltage TTL IOH = 6mA VCC = VCC Minimum IOH = 14mA VCC = VCC Minimum IOH = 20mA Commercial = 4.75V Industrial/Military = 4.5V IOL = -6mA Commercial = 4.75V Industrial/Military = 4.5V VOL Low-level Output Voltage IOL = -14mA Commercial = 4.75V Industrial/Military = 4.5V IOL = -20mA Commercial = 4.75V Industrial/Military = 4.5V IIH High-level Input Current VIN = VCC Maximum With pull-down, VIN = V CC VIN = VSS IIL Low-level Input Current With pull-up, VIN = VSS Without pull-down, VIN = VCC With pull-down, VIN = V CC Without pull-up, VIN = VSS Maximum With pull-up, VIN = VSS Maximum Standby, unprogrammed All pins 125.0 -10.0 -500.0 -250.0 0.6 -125.0 1.0 10.0 250.0 125.0 -10.0 CON = -1 mA to -250 A -250.0 CON = -1 mA to -250 A 10.0 500.0 250.0 -0.3 Ind. = 3.15 4.0 Con = 3.325 Ind. = 3.15 4.0 Con = 3.325 Ind. = 3.15 4.0 Con = 3.325 Conditions CMOS Minimum 70% VCC 2.0 -0.3 30% VCC 0.8 Typical Maximum Units V V V V V VOH High-level Output Voltage V V 0.4 V 0.4 V 0.4 10.0 500.0 V A A A A A A A A mA pF IOZH High-level Tri-state Output Leakage Current IOZL Low-level Tri-state Output Leakage Current ICC CIN Standby Current Consumption Input Capacitance 24 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AC Timing Characteristics - 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 4.75V, temperature = 70C Minimum times based on best case: VCC = 5.25V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. Cell Function Core 2-input Gate 3-input Gate 3-input Gate 4-input Gate Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry DFF DFF DFF DFF Incremental -> L Local Output Enable Local Output Enable tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPZX (Maximum) tPXZ (Maximum) x/y -> x/y x/y/z -> x/y x/y/w -> x/y x/y/w/z -> x/y y -> y x -> y y -> x x -> x w -> y w -> x z -> y z -> x q -> x/y R -> x/y S -> x/y q -> w x/y -> L oe -> L oe -> L 1.8 2.1 2.2 2.2 1.4 1.7 1.8 1.5 2.2 2.3 2.3 1.7 1.8 2.2 2.2 1.8 1.5 1.4 1.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path -2 Units Notes 25 0896C-FPGA-04/02 AC Timing Characteristics - 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 4.75V, temperature = 70C Minimum times based on best case: VCC = 5.25V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VCC. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VCC. Cell Function Repeaters Repeater Repeater Repeater Repeater Repeater Repeater tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) L -> E E -> E L -> L E -> L E -> IO L -> IO 1.3 1.3 1.3 1.3 0.8 0.8 ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path -2 Units Notes All input IO characteristics measured from a VIH of 50% at the pad (CMOS threshold) to the internal VIH of 50% of VCC. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VCC. Cell Function IO Input Input Input Input Output, Slow Output, Medium Output, Fast Output, Slow Output, Slow Output, Medium Output, Medium Output, Fast Output, Fast tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPZX (Maximum) tPXZ (Maximum) tPZX (Maximum) tPXZ (Maximum) tPZX (Maximum) tPXZ (Maximum) pad -> x/y pad -> x/y pad -> x/y pad -> x/y x/y/E/L -> pad x/y/E/L -> pad x/y/E/L -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad 1.2 3.6 7.3 10.8 5.9 4.8 3.9 6.2 1.3 4.8 1.9 3.7 1.6 ns ns ns ns ns ns ns ns ns ns ns ns ns No extra delay 1 extra delay 2 extra delays 3 extra delays 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load Parameter Path -2 Units Notes 26 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AC Timing Characteristics - 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 4.75V, temperature = 70C Minimum times based on best case: VCC = 5.25V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Path Device -2 Units Notes Global Clocks and Set/Reset GCLK Input Buffer tPD (Maximum) pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock clock -> colclk clock -> colclk clock -> colclk clock -> colclk colclk -> secclk colclk -> secclk colclk -> secclk colclk -> secclk pad -> GSRN pad -> GSRN pad -> GSRN pad -> GSRN clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 AT40K05 AT40K10 AT40K20 AT40K40 1.1 1.2 1.2 1.4 0.7 0.8 0.8 0.8 0.8 0.9 1.0 1.1 0.5 0.5 0.5 0.5 3.0 3.7 4.3 5.6 8.3 8.4 8.6 8.8 7.9 8.0 8.1 8.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rising edge clock FCLK Input Buffer tPD (Maximum) Rising edge clock Clock Column Driver tPD (Maximum) Rising edge clock Clock Sector Driver tPD (Maximum) Rising edge clock GSRN Input Buffer tPD (Maximum) From any pad to Global Set/Reset network Global Clock to Output tPD (Maximum) Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load Fast Clock to Output tPD (Maximum) 27 0896C-FPGA-04/02 AC Timing Characteristics - 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 4.75V, temperature = 70C Minimum times based on best case: VCC = 5.25V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. Cell Function Async RAM Write Write Write Write Write Write Write Write/Read Read Read Read Sync RAM Write Write Write Write Write Write Write Write Write Write/Read Read Read Read tCYC (Minimum) tCLKL (Minimum) tCLKH (Minimum) tWCS (Minimum) tWCH (Minimum) tACS (Minimum) tACH (Minimum) tDCS (Minimum) tDCH (Minimum) tCD (Maximum) tAD (Maximum) tOZX (Maximum) tOXZ (Maximum) cycle time clk clk we setup -> clk we hold -> clk wr addr setup -> clk wr addr hold -> clk wr data setup -> clk wr data hold -> clk clk -> dout rd addr -> dout oe -> dout oe -> dout 8.0 3.0 3.0 2.0 0.0 2.0 0.0 2.0 0.0 3.5 3.1 1.6 2.0 ns ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr Pulse width low Pulse width high tWECYC (Minimum) tWEL (Minimum) tWEH (Minimum) tAWS (Minimum) tAWH (Minimum) tDS (Minimum) tDH (Minimum) tDD (Maximum) tAD (Maximum) tOZX (Maximum) tOXZ (Maximum) cycle time we we wr addr setup -> we wr addr hold -> we din setup -> we din hold -> we din -> dout rd addr -> dout oe -> dout oe -> dout 8.0 3.0 3.0 2.0 0.0 2.0 0.0 4.6 3.1 1.6 2.0 ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr Pulse width low Pulse width high Parameter Path -2 Units Notes 28 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA FreeRAM Asynchronous Timing Characteristics Single-port Write/Read tWEL WE tAWS 0 1 tAWH 2 3 ADDR OE tOXZ DATA tDS tOH tDH tOZX tAD Dual-port Write with Read tWEL WE tAWS 0 1 tWECYC tWEH tAWH 2 WR ADDR tDH WR DATA PREV. NEW tDD RD ADDR = WR ADDR 1 tWD PREV. NEW RD DATA OLD Dual-port Read RD ADDR 0 1 OE tOZX tAD tOXZ DATA 29 0896C-FPGA-04/02 FreeRAM Synchronous Timing Characteristics Single-port Write/Read tCLKH CLK tWCS WE tACS ADDR 0 1 tWCH tACH 2 3 OE tOXZ DATA tDCS tDCH tOZX tAD Dual-port Write with Read tCLKH CLK tWCS WE tACS WR ADDR 0 1 tCYC tCLKL tWCH tACH 2 tDCS WR DATA tDCH RD ADDR = WR ADDR 1 tCD RD DATA Dual-port Read RD ADDR 0 1 OE tOZX tAD tOXZ DATA 30 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Absolute Maximum Ratings - 3.3V Commercial/Industrial* AT40KLV Operating Temperature.................................. -55C to +125 C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground .................................-0.5V to V CC +7V Supply Voltage (VCC ) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 250C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. DC and AC Operating Range - 3.3V Operation AT40KLV Commercial Operating Temperature (Case) VCC Power Supply Input Voltage Level (CMOS) High (VIHC) Low (VILC) 0C - 70C 3.3V 0.3V 70% - 100% VCC 0 - 30% VCC Industrial -40C - 85C 3.3V 0.3V 70% - 100% VCC 0 - 30% V CC 31 0896C-FPGA-04/02 DC Characteristics - 3.3V Operation Commercial/Industrial AT40KLV Symbol VIH Parameter High-level Input Voltage TTL CMOS VIL Low-level Input Voltage TTL IOH = 4 mA VCC = VCC Minimum VOH High-level Output Voltage IOH = 12 mA VCC = 3.0V IOH = 16 mA VCC = 3.0V IOL = -4 mA VCC = 3.0V VOL Low-level Output Voltage IOL = -12 mA VCC = 3.0V IOL = -16 mA VCC = 3.0V IIH High-level Input Current VIN = VCC Maximum With pull-down, VIN = V CC Low-level Input Current VIN = VSS With pull-up, VIN = VSS High-level Tri-state Output Leakage Current Without pull-down, VIN = VCC Maximum With pull-down, VIN = VCC Maximum Without pull-up, VIN = VSS With pull-up, VIN = VSS Standby, unprogrammed All pins 75.0 -10.0 CON = -500 A TO -125 A -150.0 0.6 CON = -500 A TO -125 A1.0 10.0 150.0 75.0 -10.0 -300.0 -150.0 -75.0 10.0 300.0 150.0 -0.3 2.1 2.1 2.1 0.4 0.4 0.4 10.0 300.0 Conditions CMOS Minimum 70% VCC 2.0 -0.3 30% VCC 0.8 Typical Maximum Units V V V V V V V V V V A A A A A A mA A mA pF IIL IOZH IOZL ICC CIN Note: Low-level Tri-state Output Leakage Current Standby Current Consumption Input Capacitance 1. Parameter based on characterization and simulation; it is not tested in production. 32 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AC Timing Characteristics - 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 3.00V, temperature = 70C Minimum times based on best case: VCC = 3.60V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. Cell Function Core 2-input Gate 3-input Gate 3-input Gate 4-input Gate Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry Fast Carry DFF DFF DFF DFF Incremental -> L Local Output Enable Local Output Enable tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPZX (Maximum) tPXZ (Maximum) x/y -> x/y x/y/z -> x/y x/y/w -> x/y x/y/w/z -> x/y y -> y x -> y y -> x x -> x w -> y w -> x z -> y z -> x q -> x/y R -> x/y S -> x/y q -> w x/y -> L oe -> L oe -> L 2.9 2.8 3.4 3.4 2.3 2.9 3.0 2.3 3.4 3.4 3.4 2.4 2.8 3.2 3.0 2.7 2.4 2.8 2.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path -3 Units Notes 33 0896C-FPGA-04/02 AC Timing Characteristics - 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 3.0V, temperature = 70C Minimum times based on best case: VCC = 3.6V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Repeaters Repeater Repeater Repeater Repeater Repeater Repeater tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) L -> E E -> E L -> L E -> L E -> IO L -> IO 2.2 2.2 2.2 2.2 1.4 1.4 ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path -3 Units Notes All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function IO Input Input Input Input Output, Slow Output, Medium Output, Fast Output, Slow Output, Slow Output, Medium Output, Medium Output, Fast Output, Fast tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPD (Maximum) tPZX (Maximum) tPXZ (Maximum) tPZX (Maximum) tPXZ (Maximum) tPZX (Maximum) tPXZ (Maximum) pad -> x/y pad -> x/y pad -> x/y pad -> x/y x/y/E/L -> pad x/y/E/L -> pad x/y/E/L -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad 1.9 5.8 11.5 17.4 9.1 7.6 6.2 9.5 2.1 7.4 2.7 5.9 2.4 ns ns ns ns ns ns ns ns ns ns ns ns ns No extra delay 1 extra delay 2 extra delays 3 extra delays 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load Parameter Path -3 Units Notes 34 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AC Timing Characteristics - 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 3.0V, temperature = 70C Minimum times based on best case: VCC = 3.6V, temperature = 0C Maximum delays are the average of tPDLH and tPDHL. Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Path Device -3 Units Notes Global Clocks and Set/Reset GCK Input Buffer tPD (Maximum) pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock pad -> clock clock -> colclk clock -> colclk clock -> colclk clock -> colclk colclk -> secclk colclk -> secclk colclk -> secclk colclk -> secclk pad -> GSRN pad -> GSRN pad -> GSRN pad -> GSRN clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out clock pad -> out AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV AT40K05LV AT40K10LV AT40K20LV AT40K40LV 1.3 1.5 1.6 1.9 0.7 0.8 0.8 0.9 1.5 1.8 2.0 2.5 1.0 1.0 1.0 1.0 4.5 5.4 6.3 8.2 13.0 13.4 13.8 14.5 12.4 12.7 13.0 13.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load Rising edge clock FCK Input Buffer tPD (Maximum) Rising edge clock Clock Column Driver tPD (Maximum) Rising edge clock Clock Sector Driver tPD (Maximum) Rising edge clock GSRN Input Buffer tPD (Maximum) Global Clock to Output tPD (Maximum) Fast Clock to Output tPD (Maximum) 35 0896C-FPGA-04/02 AC Timing Characteristics - 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 3.0V, temperature = 70C Minimum times based on best case: VCC = 3.6V, temperature = 0C Cell Function Async RAM Write Write Write Write Write Write Write Write/Read Read Read Read Sync RAM Write Write Write Write Write Write Write Write Write Write/Read Read Read Read Notes: 1. 2. 3. 4. tCYC (Minimum) tCLKL (Minimum) tCLKH (Minimum) tWCS(Minimum) tWCH (Minimum) tACS (Minimum) tACH (Minimum) tDCS (Minimum) tDCH (Minimum) tCD (Maximum) tAD (Maximum) tOZX (Maximum) tOXZ (Maximum) cycle time clk clk we setup -> clk we hold -> clk wr addr setup -> clk wr addr hold -> clk wr data setup -> clk wr data hold -> clk clk -> dout rd addr -> dout oe -> dout oe -> dout 12.0 5.0 5.0 3.2 0.0 5.0 0.0 3.9 0.0 5.8 6.3 2.9 3.5 ns ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr Pulse width low Pulse width high tWECYC (Minimum) tWEL (Minimum) tWEH (Minimum) tAWS (Minimum) tAWH (Minimum) tDS (Minimum) tDH (Minimum) tDD (Maximum) tAD (Maximum) tOZX (Maximum) tOXZ (Maximum) cycle time we we wr addr setup -> we wr addr hold -> we din setup -> we din hold -> we din -> dout rd addr -> dout oe -> dout oe -> dout 12.0 5.0 5.0 5.3 0.0 5.0 0.0 8.7 6.3 2.9 3.5 ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr Pulse width low Pulse width high Parameter Path -3 Units Notes CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and simulation; not tested in production. Exact power calculation is available in Atmel FPGA Designer software. 36 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O GND I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) AT40K10 AT40K10LV 192 I/O GND I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) AT40K20 AT40K20LV 256 I/O GND I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) AT40K40 AT40K40LV 384 I/O GND I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) GND I/O7 I/O8 I/O9 I/O10 I/O7 I/O8 VCC GND I/O11 I/O12 VCC GND I/O13 I/O14 I/O7 I/O8 I/O7 I/O8 I/O9 I/O10 I/O9 I/O10 I/O11 I/O12 I/O15 I/O16 I/O17 I/O18 GND I/O19 I/O20 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 GND I/O9, FCK1 I/O10 GND I/O13, FCK1 I/O14 GND I/O17, FCK1 I/O18 I/O21 I/O22 I/O23 I/O24 GND I/O25, FCK1 I/O26 8 9 10 10 11 12 14 15 16 14 15 16 12 13 291 290 289 288 287 286 285 H23 H24 G25 G26 GND(1) J23 J24 8 9 10 11 12 13 8 9 10 11 295 294 293 292 D26 G24 F25 F26 297 296 D25 F23 F24 E25 VCC(1) GND(1) 15 16 7 8 4 5 84 PLCC 12 13 100 PQFP 4 5 100 TQFP 1 2 Left Side (Top to Bottom) 144 LQFP 1 2 160 PQFP 1 2 208 PQFP 2 4 240 PQFP 1 2 304 PQFP(2) 304 303 352 SBGA(2) GND(1) D23 14 6 3 3 4 5 6 7 3 4 5 6 7 5 6 7 8 9 3 4 5 6 7 302 301 300 299 298 C25 D24 E23 C26 E24 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 37 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O I/O11 (A20) I/O12 (A21) AT40K10 AT40K10LV 192 I/O I/O15 (A20) I/O16 (A21) VCC I/O17 I/O18 AT40K20 AT40K20LV 256 I/O I/O19 (A20) I/O20 (A21) VCC I/O21 I/O22 AT40K40 AT40K40LV 384 I/O I/O27 (A20) I/O28 (A21) VCC I/O29 I/O30 GND I/O31 I/O32 I/O33 I/O34 84 PLCC 17 18 100 PQFP 9 10 100 TQFP 6 7 Left Side (Top to Bottom) 144 LQFP 11 12 160 PQFP 13 14 208 PQFP 17 18 240 PQFP 17 18 19 20 21 304 PQFP(2) 284 283 282 280 279 352 SBGA(2) H25 K23 VCC(1) K24 J25 J26 L23 278 277 22 L24 K25 GND(1) VCC(1) I/O23 I/O24 GND I/O35 I/O36 GND VCC I/O37 I/O38 I/O25 I/O26 I/O19 I/O20 I/O27 I/O28 I/O39 I/O40 I/O41 I/O42 GND 19 20 23 24 276 275 274 273 L25 L26 M23 M24 I/O13 I/O14 I/O21 I/O22 I/O29 I/O30 I/O43 I/O44 I/O45 I/O46 11 8 13 14 15 16 21 22 25 26 272 271 M25 M26 I/O15 (A22) I/O16 (A23) GND VCC I/O17 I/O18 I/O23 (A22) I/O24 (A23) GND VCC I/O25 I/O26 I/O31 (A22) I/O32 (A23) GND VCC I/O33 I/O34 I/O47 (A22) I/O48 (A23) GND VCC I/O49 I/O50 I/O51 I/O52 19 20 21 22 23 24 12 13 14 15 16 17 9 10 11 12 13 14 15 16 17 18 19 20 17 18 19 20 21 22 23 24 25 26 27 28 27 28 29 30 31 32 270 269 268 267 266 265 N24 N25 GND(1) VCC(1) N26 P25 I/O19 I/O27 I/O35 I/O53 18 15 21 23 29 33 264 P23 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 38 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O I/O20 AT40K10 AT40K10LV 192 I/O I/O28 AT40K20 AT40K20LV 256 I/O I/O36 AT40K40 AT40K40LV 384 I/O I/O54 GND I/O29 I/O30 I/O37 I/O38 I/O39 I/O40 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 VCC GND I/O41 I/O42 GND I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 GND I/O31 I/O32 VCC I/O21 I/O22 I/O23 I/O24, FCK2 GND I/O33 I/O34 I/O35 I/O36, FCK2 GND I/O43 I/O44 VCC I/O45 I/O46 I/O47 I/O48, FCK2 GND I/O49 I/O50 I/O37 I/O38 I/O51 I/O52 I/O67 I/O68 VCC I/O69 I/O70 I/O71 I/O72, FCK2 GND I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 GND I/O79 I/O80 I/O39 I/O40 I/O53 I/O54 I/O81 I/O82 38 39 48 49 243 242 AA26 Y25 46 47 25 26 19 20 16 17 23 24 25 26 27 25 26 27 28 29 33 34 35 36 37 38 39 40 41 42 43 44 45 256 255 253 252 251 250 249 248 247 246 245 244 T23 V26 VCC(1) U24 V25 V24 U23 GND(1) Y26 W25 W24 V23 T24 U25 37 258 257 VCC(1) GND(1) T26 T25 31 32 35 36 262 261 260 259 R26 R25 R24 R23 84 PLCC 100 PQFP 100 TQFP Left Side (Top to Bottom) 144 LQFP 22 160 PQFP 24 208 PQFP 30 240 PQFP 34 304 PQFP(2) 263 352 SBGA(2) P24 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 39 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O I/O25 I/O26 AT40K10 AT40K10LV 192 I/O I/O41 I/O42 AT40K20 AT40K20LV 256 I/O I/O55 I/O56 GND VCC I/O57 I/O58 AT40K40 AT40K40LV 384 I/O I/O83 I/O84 GND VCC I/O85 I/O86 I/O87 I/O88 84 PLCC 100 PQFP 100 TQFP Left Side (Top to Bottom) 144 LQFP 160 PQFP 30 31 208 PQFP 40 41 240 PQFP 50 51 304 PQFP(2) 241 240 352 SBGA(2) Y24 AA25 GND(1) VCC(1) 239 238 AB25 AA24 I/O27 I/O28 I/O43 I/O44 I/O59 I/O60 I/O89 I/O90 GND I/O91 I/O92 27 21 22 18 19 28 29 32 33 42 43 52 53 237 236 Y23 AC26 AD26 AC25 30 31 28 23 20 32 34 35 36 44 45 46 54 55 56 235 234 233 AA23 AB24 AD25 I/O29 I/O30 I/O31 (OTS)(3) I/O32, GCK2 M1 GND M0 I/O45 I/O46 I/O47 (OTS)(3) I/O48, GCK2 M1 GND M0 I/O61 I/O62 I/O63 (OTS)(3) I/O64, GCK2 M1 GND M0 I/O93 I/O94 I/O95 (OTS)(3) I/O96, GCK2 M1 GND M0 29 30 31 32 24 25 26 27 21 22 23 24 33 34 35 36 37 38 39 40 47 48 49 50 57 58 59 60 232 231 230 229 AC24 AB23 GND(1) AD24 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. AT40K05 AT40K05LV 128 I/O VCC M2 I/O33, GCK3 I/O34 (HDC) I/O35 I/O36 I/O37 AT40K10 AT40K10LV 192 I/O VCC M2 I/O49, GCK3 I/O50 (HDC) I/O51 I/O52 I/O53 AT40K20 AT40K20LV 256 I/O VCC M2 I/O65, GCK3 I/O66 (HDC) I/O67 I/O68 I/O69 AT40K40 AT40K40LV 384 I/O VCC M2 I/O97, GCK3 I/O98 (HDC) I/O99 I/O100 I/O101 32 29 84 PLCC 33 34 35 36 100 PQFP 28 29 30 31 100 TQFP 25 26 27 28 Bottom Side (Left to Right) 144 LQFP 37 38 39 40 41 42 43 160 PQFP 41 42 43 44 45 46 47 208 PQFP 55 56 57 58 59 60 61 240 PQFP 61 62 63 64 65 66 67 304 PQFP(2) 228 227 226 225 224 223 222 352 SBGA(2) VCC(1) AC23 AE24 AD23 AC22 AF24 AD22 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 40 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O I/O38 (LDC) AT40K10 AT40K10LV 192 I/O I/O54 (LDC) AT40K20 AT40K20LV 256 I/O I/O70 (LDC) AT40K40 AT40K40LV 384 I/O I/O102 (LDC) GND I/O103 I/O104 I/O105 I/O106 I/O71 I/O72 VCC GND I/O39 I/O40 I/O55 I/O56 I/O57 I/O58 I/O73 I/O74 I/O75 I/O76 I/O107 I/O108 VCC GND I/O109 I/O110 I/O111 I/O112 I/O113 I/O114 GND I/O77 I/O78 I/O59 I/O60 I/O79 I/O80 I/O115 I/O116 I/O117 I/O118 I/O119 I/O120 GND I/O41 I/O42 I/O43 I/O44 GND I/O61 I/O62 I/O63 I/O64 VCC I/O65 I/O66 GND I/O81 I/O82 I/O83 I/O84 VCC I/O85 I/O86 GND I/O121 I/O122 I/O123 I/O124 VCC I/O125 I/O126 GND I/O127 I/O128 I/O129 I/O130 AC16 AD16 72 73 38 39 34 35 31 32 45 46 47 48 49 51 52 53 54 55 67 68 69 70 71 75 76 77 78 79 80 81 82 73 74 214 213 212 211 210 209 208 207 206 204 203 202 AD19 AE20 AF20 AC18 GND(1) AD18 AE19 AC17 AD17 VCC(1) AE18 AF18 49 50 63 64 65 66 69 70 71 72 218 217 216 215 220 219 AC21 AD21 AE22 AF23 VCC(1) GND(1) AD20 AE21 AF21 AC19 84 PLCC 37 100 PQFP 33 100 TQFP 30 Bottom Side (Left to Right) 144 LQFP 44 160 PQFP 48 208 PQFP 62 240 PQFP 68 304 PQFP(2) 221 352 SBGA(2) AE23 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 41 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O I/O87 I/O88 GND AT40K40 AT40K40LV 384 I/O I/O131 I/O132 GND VCC 84 PLCC 100 PQFP 100 TQFP Bottom Side (Left to Right) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 201 200 83 352 SBGA(2) AE17 AE16 GND(1) VCC(1) 199 198 84 85 36 37 33 34 50 51 56 57 74 75 86 87 197 196 195 194 AF16 AC15 AD15 AE15 AF15 AD14 I/O89 I/O90 I/O67 I/O68 I/O45 I/O46 I/O69 I/O70 I/O91 I/O92 I/O93 I/O94 I/O133 I/O134 I/O135 I/O136 I/O137 I/O138 GND I/O139 I/O140 I/O141 I/O142 I/O47 (D15) I/O48 (INIT) VCC GND I/O49 (D14) I/O50 (D13) I/O71 (D15) I/O72 (INIT) VCC GND I/O73 (D14) I/O74 (D13) I/O95 (D15) I/O96 (INIT) VCC GND I/O97 (D14) I/O98 (D13) I/O143 (D15) I/O144 (INIT) VCC GND I/O145 (D14) I/O146 (D13) I/O147 I/O148 I/O149 I/O150 GND 40 41 42 43 44 45 38 39 40 41 42 43 35 36 37 38 39 40 52 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 88 89 90 91 92 93 193 192 191 190 189 188 AE14 AF14 VCC(1) GND(1) AE13 AC13 I/O51 I/O52 I/O75 I/O76 I/O77 I/O78 I/O99 I/O100 I/O101 I/O102 I/O103 I/O104 I/O151 I/O152 I/O153 I/O154 I/O155 I/O156 VCC 44 45 41 42 58 59 64 65 82 83 84 85 94 95 96 97 187 186 185 184 183 182 AD13 AF12 AE12 AD12 AC12 AF11 VCC(1) GND I/O105 GND I/O157 98 181 GND(1) AE11 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 42 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O I/O106 AT40K40 AT40K40LV 384 I/O I/O158 I/O159 I/O160 I/O161 I/O162 GND I/O79 I/O80 VCC I/O53 (D12) I/O54 (D11) I/O55 I/O56 GND I/O81 (D12) I/O82 (D11) I/O83 I/O84 GND I/O107 I/O108 VCC I/O109 (D12) I/O110 (D11) I/O111 I/O112 GND I/O113 I/O114 I/O85 I/O86 I/O115 I/O116 I/O163 I/O164 VCC I/O165 (D12) I/O166 (D11) I/O167 I/O168 GND I/O169 I/O170 I/O171 I/O172 I/O173 I/O174 GND I/O175 I/O176 I/O87 I/O88 I/O57 I/O58 I/O89 I/O90 I/O117 I/O118 I/O119 I/O120 GND VCC I/O121 I/O122 I/O59 (D10) I/O60 (D9) I/O91 (D10) I/O92 (D9) I/O123 (D10) I/O124 (D9) I/O177 I/O178 I/O179 I/O180 GND VCC I/O181 I/O182 I/O183 (D10) I/O184 (D9) I/O185 I/O186 48 49 48 49 45 46 65 66 73 74 95 96 113 114 162 161 160 159 71 72 91 92 93 94 109 110 111 112 166 165 164 163 AE7 AD7 AE6 AE5 GND(1) VCC(1) AD6 AC7 AF4 AF3 AE4 AC6 107 108 46 47 46 47 43 44 60 61 62 63 64 66 67 68 69 70 86 87 88 89 90 99 100 101 102 103 104 105 106 179 178 177 175 174 173 172 171 170 169 168 167 AF9 AD10 VCC(1) AE9 AD9 AC10 AF7 GND(1) AE8 AD8 AC9 AF6 84 PLCC 100 PQFP 100 TQFP Bottom Side (Left to Right) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 180 352 SBGA(2) AD11 AE10 AC11 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 43 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O AT40K40 AT40K40LV 384 I/O GND I/O187 I/O188 84 PLCC 100 PQFP 100 TQFP Bottom Side (Left to Right) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 352 SBGA(2) I/O61 I/O62 I/O63 (D8) I/O64, GCK4 GND CON I/O93 I/O94 I/O95 (D8) I/O96, GCK4 GND CON I/O125 I/O126 I/O127 (D8) I/O128, GCK4 GND CON I/O189 I/O190 I/O191 (D8) I/O192, GCK4 GND CON 50 51 52 53 50 51 52 53 47 48 49 50 67 68 69 70 71 72 75 76 77 78 79 80 97 98 99 100 101 103 115 116 117 118 119 120 158 157 156 155 154 153 AD5 AE3 AD4 AC5 GND(1) AD3 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. AT40K05 AT40K05LV 128 I/O VCC RESET I/O65 (D7) I/O66, GCK5 I/O67 I/O68 AT40K10 AT40K10LV 192 I/O VCC RESET I/O97 (D7) I/O98, GCK5 I/O99 I/O100 AT40K20 AT40K20LV 256 I/O VCC RESET I/O129 (D7) I/O130, GCK5 I/O131 I/O132 I/O133 I/O134 AT40K40 AT40K40LV 384 I/O VCC RESET I/O193 (D7) I/O194, GCK5 I/O195 I/O196 I/O197 I/O198 GND 84 PLCC 54 55 56 57 100 PQFP 54 55 56 57 100 TQFP 51 52 53 54 Right Side (Bottom to Top) 144 LQFP 73 74 75 76 77 78 160 PQFP 81 82 83 84 85 86 208 PQFP 106 108 109 110 111 112 240 PQFP 121 122 123 124 125 126 304 PQFP(2) 152 151 150 149 148 147 352 SBGA(2) VCC(1) AC4 AD2 AC3 AB4 AD1 AB3 AC2 I/O101 I/O102 I/O135 I/O136 I/O199 I/O200 I/O201 I/O202 I/O203 I/O204 127 128 146 145 AA4 AA3 144 143 AB2 AC1 VCC(1) GND(1) VCC GND I/O69 (D6) I/O103 (D6) I/O137 (D6) VCC GND I/O205 (D6) 58 58 55 79 87 113 129 142 Y3 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 44 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O I/O70 I/O71 I/O72 AT40K10 AT40K10LV 192 I/O I/O104 I/O105 I/O106 AT40K20 AT40K20LV 256 I/O I/O138 I/O139 I/O140 AT40K40 AT40K40LV 384 I/O I/O206 I/O207 I/O208 I/O209 I/O210 GND I/O211 I/O212 I/O107 I/O108 I/O141 I/O142 I/O143 I/O144 GND GND I/O109 I/O110 I/O73, FCK3 I/O74 I/O111, FCK3 I/O112 VCC I/O75 (D5) I/O76 (CS0) I/O113 (D5) I/O114 (CS0) GND I/O145 I/O146 I/O147, FCK3 I/O148 VCC I/O149 (D5) I/O150 (CS0) I/O213 I/O214 I/O215 I/O216 GND I/O217 I/O218 I/O219, FCK3 I/O220 VCC I/O221 (D5) I/O222 (CS0) GND I/O223 I/O224 I/O225 I/O226 I/O151 I/O152 GND I/O227 I/O228 GND VCC I/O229 I/O230 I/O153 I/O154 I/O115 I/O116 I/O155 I/O156 I/O231 I/O232 I/O233 I/O234 124 125 144 145 123 122 121 120 T1 R4 R3 R2 143 125 124 U2 T2 GND(1) VCC(1) T4 T3 59 60 60 61 57 58 84 85 94 95 122 123 82 83 92 93 120 121 81 91 119 135 136 137 138 139 140 141 142 117 118 133 134 138 137 136 135 134 133 132 131 130 129 127 126 W3 Y2 Y1 V4 GND(1) V3 W2 U4 U3 VCC(1) V2 V1 84 PLCC 100 PQFP 59 100 TQFP 56 Right Side (Bottom to Top) 144 LQFP 80 160 PQFP 88 89 90 208 PQFP 114 115 116 240 PQFP 130 131 132 304 PQFP(2) 141 140 139 352 SBGA(2) AA2 AA1 W4 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 45 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O AT40K40 AT40K40LV 384 I/O GND 84 PLCC 100 PQFP 100 TQFP Right Side (Bottom to Top) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 352 SBGA(2) I/O77 I/O78 I/O117 I/O118 I/O157 I/O158 I/O235 I/O236 I/O237 I/O238 62 63 59 60 86 87 96 97 126 127 146 147 119 118 R1 P3 I/O79(D4) I/O80 VCC GND I/O81 (D3) I/O82 (CHECK) I/O119(D4) I/O120 VCC GND I/O121 (D3) I/O122 (CHECK) I/O159(D4) I/O160 VCC GND I/O161 (D3) I/O162 (CHECK) I/O239(D4) I/O240 VCC GND I/O241 (D3) I/O242 (CHECK) I/O243 I/O244 61 62 63 64 65 64 65 66 67 68 61 62 63 64 65 88 89 90 91 92 98 99 100 101 102 128 129 130 131 132 148 149 150 151 152 117 116 115 114 113 P2 P1 VCC(1) GND(1) N2 66 69 66 93 103 133 153 112 N4 I/O83 I/O84 I/O123 I/O124 I/O163 I/O164 I/O245 I/O246 GND 70 67 94 95 104 105 134 135 154 155 111 110 N3 M1 I/O125 I/O126 I/O165 I/O166 I/O167 I/O168 I/O247 I/O248 I/O249 I/O250 I/O251 I/O252 VCC 136 137 156 157 109 108 107 106 M2 M3 M4 L1 VCC(1) 158 105 104 GND(1) L2 L3 K2 L4 GND I/O169 I/O170 GND I/O253 I/O254 I/O255 I/O256 I/O257 I/O258 GND I/O85 (D2) I/O86 I/O127 (D2) I/O128 VCC I/O171 (D2) I/O172 VCC I/O173 I/O259 (D2) I/O260 VCC I/O261 67 68 71 72 68 69 96 97 106 107 138 139 159 160 161 103 102 101 99 J1 K3 VCC(1) J2 I/O87 I/O129 98 108 140 162 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 46 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O I/O88, FCK4 AT40K10 AT40K10LV 192 I/O I/O130, FCK4 I/O131 I/O132 GND GND AT40K20 AT40K20LV 256 I/O I/O174, FCK4 I/O175 I/O176 GND I/O177 I/O178 I/O133 I/O134 I/O179 I/O180 AT40K40 AT40K40LV 384 I/O I/O262, FCK4 I/O263 I/O264 GND I/O265 I/O266 I/O267 I/O268 I/O269 I/O270 GND I/O135 I/O136 I/O89 I/O90 I/O137 I/O138 I/O181 I/O182 I/O183 I/O184 I/O271 I/O272 I/O273 I/O274 I/O275 I/O276 GND VCC I/O91 (D1) I/O92 I/O139 (D1) I/O140 I/O185 (D1) I/O186 GND VCC I/O277 (D1) I/O278 I/O279 I/O280 I/O281 I/O282 GND I/O187 I/O188 I/O93 I/O94 I/O95 (D0) I/O96, GCK6 (CSOUT) I/O141 I/O142 I/O143 (D0) I/O144, GCK6 (CSOUT) I/O189 I/O190 I/O191 (D0) I/O192, GCK6 (CSOUT) I/O283 I/O284 I/O285 I/O286 I/O287 (D0) I/O288, GCK6 (CSOUT) 72 76 73 106 118 152 178 79 E4 71 75 72 103 104 105 115 116 117 149 150 151 175 176 177 84 83 82 81 80 D2 F4 E3 C2 D3 69 70 73 74 70 71 101 102 113 114 147 148 173 174 86 85 GND(1) VCC(1) F3 G4 D1 C1 111 112 143 144 145 146 169 170 171 172 90 89 88 87 G2 G3 F2 E2 167 168 100 110 142 84 PLCC 100 PQFP 100 TQFP Right Side (Bottom to Top) 144 LQFP 99 160 PQFP 109 208 PQFP 141 240 PQFP 163 164 165 166 304 PQFP(2) 98 97 96 95 94 93 92 91 352 SBGA(2) J3 K4 G1 GND(1) H2 H3 J4 F1 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 47 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O CCLK VCC TSTCLK AT40K10 AT40K10LV 192 I/O CCLK VCC TSTCLK AT40K20 AT40K20LV 256 I/O CCLK VCC TSTCLK AT40K40 AT40K40LV 384 I/O CCLK VCC TSTCLK 84 PLCC 73 74 75 100 PQFP 77 78 79 100 TQFP 74 75 76 Right Side (Bottom to Top) 144 LQFP 107 108 109 160 PQFP 119 120 121 208 PQFP 153 154 159 240 PQFP 179 180 181 304 PQFP(2) 78 77 76 352 SBGA(2) C3 VCC(1) D4 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. AT40K05 AT40K05LV 128 I/O GND I/O97 (A0) I/O98, GCK7 (A1) I/O99 I/O100 AT40K10 AT40K10LV 192 I/O GND I/O145 (A0) I/O146, GCK7 (A1) I/O147 I/O148 AT40K20 AT40K20LV 256 I/O GND I/O193 (A0) I/O194, GCK7 (A1) I/O195 I/O196 AT40K40 AT40K40LV 384 I/O GND I/O289 (A0) I/O290, GCK7 (A1) I/O291 I/O292 I/O293 I/O294 GND I/O295 I/O296 84 PLCC 76 77 100 PQFP 80 81 100 TQFP 77 78 Top Side (Right to Left) 144 LQFP 110 111 160 PQFP 122 123 208 PQFP 160 161 240 PQFP 182 183 304 PQFP(2) 75 74 352 SBGA(2) GND(1) B3 78 82 79 112 113 114 124 125 126 162 163 164 184 185 186 73 72 71 C4 D5 A3 C5 B4 79 83 80 115 127 165 187 70 D6 I/O101 (CS1,A2) I/O102 (A3) I/O149 (CS1,A2) I/O150 (A3) I/O197 (CS1,A2) I/O198 (A3) I/O199 I/O200 VCC GND I/O297 (CS1,A2) I/O298 (A3) I/O299 I/O300 VCC GND I/O301 (3) I/O302 I/O303 I/O304 I/O305 I/O306 GND 80 84 81 116 128 166 188 69 68 67 C6 B5 A4 VCC(1) GND(1) I/O151 (3) I/O152 I/O103 I/O104(3) I/O153 I/O154 I/O201 (3) I/O202 I/O203 I/O204 75(3) NC 79(3) NC 76(3) NC 109(3) NC 121 (3) NC 159 (3) NC 189 (3) NC 190 66 (3) NC 65 64 63 C7 (3) NC B6 A6 D8 C8 117 129 130 167 168 191 192 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 48 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O AT40K40 AT40K40LV 384 I/O I/O307 I/O308 I/O155 I/O156 I/O205 I/O206 I/O207 I/O208 GND I/O105 I/O106 GND I/O157 I/O158 I/O159 I/O160 VCC GND I/O209 I/O210 I/O211 I/O212 VCC I/O213 I/O214 I/O309 I/O310 I/O311 I/O312 GND I/O313 I/O314 I/O315 I/O316 VCC I/O317 I/O318 GND I/O319 I/O320 I/O321 I/O322 I/O215 I/O216 GND I/O323 I/O324 GND VCC I/O107 (A4) I/O108 (A5) I/O161 (A4) I/O162 (A5) I/O163 I/O164 I/O109 I/O110 I/O165 I/O166 I/O217 (A4) I/O218 (A5) I/O219 I/O220 I/O221 I/O222 I/O325 (A4) I/O326 (A5) I/O327 I/O328 I/O329 I/O330 GND I/O331 I/O332 I/O333 I/O334 I/O111 (A6) I/O167 (A6) I/O223 (A6) I/O335 (A6) 83 89 86 125 139 180 209 41 A13 87 88 84 85 123 124 136 137 138 81 82 85 86 82 83 121 122 134 135 174 175 176 177 178 179 202 203 205 206 207 208 47 46 45 44 43 42 49 48 C11 B10 B11 A11 GND(1) VCC(1) D12 C12 B12 A12 C13 B13 118 119 120 131 132 133 171 172 173 196 197 198 199 200 201 169 170 193 194 195 62 61 60 59 58 57 56 55 54 52 51 50 B7 A7 D9 C9 GND(1) B8 D10 C10 B9 VCC(1) A9 D11 84 PLCC 100 PQFP 100 TQFP Top Side (Right to Left) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 352 SBGA(2) Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 49 0896C-FPGA-04/02 AT40K05 AT40K05LV 128 I/O I/O112 (A7) GND VCC I/O113 (A8) I/O114 (A9) AT40K10 AT40K10LV 192 I/O I/O168 (A7) GND VCC I/O169 (A8) I/O170 (A9) AT40K20 AT40K20LV 256 I/O I/O224 (A7) GND VCC I/O225 (A8) I/O226 (A9) AT40K40 AT40K40LV 384 I/O I/O336 (A7) GND VCC I/O337 (A8) I/O338 (A9) I/O339 I/O340 I/O341 I/O342 GND 84 PLCC 84 1 2 3 4 100 PQFP 90 91 92 93 94 100 TQFP 87 88 89 90 91 Top Side (Right to Left) 144 LQFP 126 127 128 129 130 160 PQFP 140 141 142 143 144 208 PQFP 181 182 183 184 185 240 PQFP 210 211 212 213 214 304 PQFP(2) 40 39 38 37 36 352 SBGA(2) B14 GND(1) VCC(1) D14 C14 I/O115 I/O116 I/O171 I/O172 I/O173 I/O174 I/O227 I/O228 I/O229 I/O230 I/O231 (A10) I/O232 (A11) I/O343 I/O344 I/O345 I/O346 I/O347 (A10) I/O348 (A11) VCC 5 6 95 96 92 93 131 132 145 146 186 187 188 189 215 216 217 218 220 221 35 34 33 32 31 30 A15 B15 C15 D15 A16 B16 VCC(1) GND(1) I/O117 (A10) I/O118 (A11) I/O175 (A10) I/O176 (A11) 97 98 94 95 133 134 147 148 190 191 GND I/O233 I/O234 GND I/O349 I/O350 I/O351 I/O352 I/O353 I/O354 GND 29 28 C16 B17 D16 A18 I/O235 I/O236 VCC I/O177 I/O178 I/O119 I/O120 GND I/O179 I/O180 GND VCC I/O237 I/O238 I/O239 I/O240 GND I/O241 I/O355 I/O356 VCC I/O357 I/O358 I/O359 I/O360 GND I/O361 135 136 137 149 150 151 192 193 194 222 223 224 225 226 227 27 26 25 23 22 21 20 19 18 C17 B18 VCC(1) C18 D17 A20 B19 GND(1) C19 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 50 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K05 AT40K05LV 128 I/O AT40K10 AT40K10LV 192 I/O AT40K20 AT40K20LV 256 I/O I/O242 I/O181 I/O182 I/O243 I/O244 AT40K40 AT40K40LV 384 I/O I/O362 I/O363 I/O364 I/O365 I/O366 GND I/O367 I/O368 I/O121 I/O122 I/O123 (A12) I/O124 (A13) I/O183 I/O184 I/O185 (A12) I/O186 (A13) I/O245 I/O246 I/O247 (A12) I/O248 (A13) GND VCC I/O249 I/O250 I/O369 I/O370 I/O371 (A12) I/O372 (A13) GND VCC I/O373 I/O374 I/O375 I/O376 I/O377 I/O378 GND I/O187 I/O188 I/O125 I/O126 I/O127 (A14) I/O128, GCK8 (A15) VCC I/O189 I/O190 I/O191 (A14) I/O192, GCK8 (A15) VCC I/O251 I/O252 I/O253 I/O254 I/O255 (A14) I/O256, GCK8 (A15) VCC I/O379 I/O380 I/O381 I/O382 I/O383 (A14) I/O384, GCK8 (A15) VCC 9 1 98 140 141 142 156 157 158 201 202 203 234 235 236 237 238 7 6 5 4 3 D21 C22 B24 C23 D22 9 8 7 8 99 100 96 97 138 139 152 153 154 155 197 198 199 200 230 231 232 233 14 13 12 10 C20 B21 B22 C21 GND(1) VCC(1) D20 A23 A24 B23 195 196 228 229 84 PLCC 100 PQFP 100 TQFP Top Side (Right to Left) 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP(2) 17 16 15 352 SBGA(2) D18 A21 B20 10 11 2 3 99 100 143 144 159 160 204 205 239 240 2 1 C24 VCC(1) Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 51 0896C-FPGA-04/02 Power and Ground Pinouts for 352 SBGA(1) VCC Pins A10 G23 U26 AE25 A17 H4 W23 AF10 B2 K1 Y4 AF17 GND Pins A1 A25 H26 AE1 AF19 Note: A2 A26 N1 AE26 AF22 A5 B1 P26 AF1 AF25 A8 B26 W1 AF2 AF26 A14 E1 W26 AF5 A19 E26 AB1 AF8 A22 H1 AB26 AF13 B25 K26 AC8 D7 N23 AC14 D13 P4 AC20 D19 U1 AE2 1. In SBGA packages, Power and Ground pins do not connect directly to die. They connect to Power and Ground planes inside the package. 52 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA Part/Package Availability and User I/O Counts (including Dual-function Pins) Package(1) 84 PLCC 100 PQFP 100 TQFP 144 LQFP 160 PQFP 208 PQFP 240 PQFP 304 PQFP 352 SBGA Note: AT40K05/AT40K05LV 62 78 78 114 128 128 - - - AT40K10/AT40K10LV 62 78 78 114 130 161 - - - AT40K20/AT40K20LV 62 77 78 114 130 161 193 - - AT40K40/AT40K40LV - - - 114 - 161 193 256 289 1. Devices in same package are pin-to-pin compatible. Package Type 84J 100Q4 100T1 144L1 160Q1 208Q1 240Q1 304Q1 352C1 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Plastic Quad Flat Package (PQFP) 100-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 144-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 160-lead, Plastic Quad Flat Package (PQFP) 208-lead, Plastic Quad Flat Package (PQFP) 240-lead, Plastic Quad Flat Package (PQFP) 304-lead, Plastic Quad Flat Package (PQFP) 252-ball, Enhanced, Low-profile Square Ball Grid Array Package (SBGA) 53 0896C-FPGA-04/02 AT40K05/AT40K05LV Ordering Information Usable Gates 5,000 - 10,000 Operating Voltage 5.0V Speed Grade (ns) 2 Ordering Code AT40K05-2AJC AT40K05-2AQC AT40K05-2RQC AT40K05-2BQC AT40K05-2CQC AT40K05-2DQC AT40K05-2AJI AT40K05-2AQI AT40K05-2RQI AT40K05-2BQI AT40K05-2CQI AT40K05-2DQI AT40K05LV-3AJC AT40K05LV-3AQC AT40K05LV-3RQC AT40K05LV-3BQC AT40K05LV-3CQC AT40K05LV-3DQC AT40K05LV-3AJI AT40K05LV-3AQI AT40K05LV-3RQI AT40K05LV-3BQI AT40K05LV-3CQI AT40K05LV-3DQI Package 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 Operation Range(1) Commercial (0C to 70C) 5,000 - 10,000 5.0V 2 Industrial (-40C to 85C) 5,000 - 10,000 3.3V 3 Commercial (0C to 70C) 5,000 - 10,000 3.3V 3 Industrial (-40C to 85C) Note: 1. For military parts, contact Atmel at fpga@atmel.com. 54 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K10/AT40K10LV Ordering Information Usable Gates 10,000 - 20,000 Operating Voltage 5.0V Speed Grade (ns) 2 Ordering Code AT40K10-2AJC AT40K10-2AQC AT40K10-2RQC AT40K10-2BQC AT40K10-2CQC AT40K10-2DQC AT40K10-2AJI AT40K10-2AQI AT40K10-2RQI AT40K10-2BQI AT40K10-2CQI AT40K10-2DQI AT40K10LV-3AJC AT40K10LV-3AQC AT40K10LV-3RQC AT40K10LV-3BQC AT40K10LV-3CQC AT40K10LV-3DQC AT40K10LV-3AJI AT40K10LV-3AQI AT40K10LV-3RQI AT40K10LV-3BQI AT40K10LV-3CQI AT40K10LV-3DQI Package 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 Operation Range(1) Commercial (0C to 70C) 10,000 - 20,000 5.0V 2 Industrial (-40C to 85C) 10,000 - 20,000 3.3V 3 Commercial (0C to 70C) 10,000 - 20,000 3.3V 3 Industrial (-40C to 85C) Note: 1. For military parts, contact Atmel at fpga@atmel.com. 55 0896C-FPGA-04/02 AT40K20/AT40K20LV Ordering Information Usable Gates 20,000 - 30,000 Operating Voltage 5.0V Speed Grade (ns) 2 Ordering Code AT40K20-2AJC AT40K20-2AQC AT40K20-2RQC AT40K20-2BQC AT40K20-2CQC AT40K20-2DQC AT40K20-2EQC AT40K20-2AJI AT40K20-2AQI AT40K20-2RQI AT40K20-2BQI AT40K20-2CQI AT40K20-2DQI AT40K20-2EQI AT40K20LV-3AJC AT40K20LV-3AQC AT40K20LV-3RQC AT40K20LV-3BQC AT40K20LV-3CQC AT40K20LV-3DQC AT40K20LV-2EQC AT40K20LV-3AJI AT40K20LV-3AQI AT40K20LV-3RQI AT40K20LV-3BQI AT40K20LV-3CQI AT40K20LV-3DQI AT40K20LV-2EQI Package 84J 100T1 100Q4 144L1 160Q1 208Q1 240Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 240Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 240Q1 84J 100T1 100Q4 144L1 160Q1 208Q1 240Q1 Operation Range(1) Commercial (0C to 70C) 20,000 - 30,000 5.0V 2 Industrial (-40C to 85C) 20,000 - 30,000 3.3V 3 Commercial (0C to 70C) 20,000 - 30,000 3.3V 3 Industrial (-40C to 85C) Note: 1. For military parts, contact Atmel at fpga@atmel.com 56 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA AT40K40/AT40K40LV Ordering Information Usable Gates 40,000 - 50,000 Operating Voltage 5.0V Speed Grade (ns) 2 Ordering Code AT40K40-2BQC AT40K40-2DQC AT40K40-2EQC AT40K40-2FQC AT40K40-2BGC AT40K40-2BQI AT40K40-2DQI AT40K40-2EQI AT40K40-2FQI AT40K40-2BGI AT40K40LV-2BQC AT40K40LV-2DQC AT40K40LV-2EQC AT40K40LV-2FQC AT40K40LV-2BGC AT40K40LV-2BQI AT40K40LV-2DQI AT40K40LV-2EQI AT40K40LV-2FQI AT40K40LV-2BGI Package 144Q1 208Q1 240Q1 304Q1 352C1 144Q1 208Q1 240Q1 304Q1 352C1 144Q1 208Q1 240Q1 304Q1 352C1 144Q1 208Q1 240Q1 304Q1 352C1 Operation Range(1) Commercial (0C to 70C) 40,000 - 50,000 5.0V 2 Industrial (-40C to 85C) 40,000 - 50,000 3.3V 3 Commercial (0C to 70C) 40,000 - 50,000 3.3V 3 Industrial (-40C to 85C) Note: 1. For military parts, contact Atmel at fpga@atmel.com. 57 0896C-FPGA-04/02 Packaging Information 84J - PLCC 1.14(0.045) X 45 PIN NO. 1 IDENTIFIER 1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45 MAX (3X) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e COMMON DIMENSIONS (Unit of Measure = mm) MIN 4.191 2.286 0.508 30.099 29.210 30.099 29.210 27.686 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 30.353 29.413 30.353 29.413 28.702 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 84J REV. B R 58 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA 100T1 - TQFP D1 D XX e E1 CO E U NT RY b Bottom View Top View COMMON DIMENSIONS (Unit of Measure = mm) A2 SYMBOL A1 A2 MIN 0.05 0.95 NOM MAX 0.15 NOTE 6 1.00 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 1.05 A1 L1 D D1 E E1 e b L1 0.17 2, 3 Side View 2, 3 0.22 1.00 REF 0.27 4, 5 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions, including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body. 11/30/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 100T1, 100-lead (14 x 14 x 1.0 mm Body), Thin Plastic Quad Flat Pack (TQFP) DRAWING NO. 100T1 REV. A 59 0896C-FPGA-04/02 100Q4 - PQFP D1 D E1 E Top View Bottom View A2 A1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation GC-1, for additional information. 2. To be determined at seating plane. 3. Regardless of the relative size of the upper and lower body sections, dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold Flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. Dimension b does not include Dambar protrusion. The Dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 5. A1 is defined as the distance from the seating plane to the lowest point of the package body. SYMBOL A1 A2 D D1 E E1 e b L1 MIN 0.25 2.50 NOM - 2.70 23.20 BSC 20.00 BSC 17.20 BSC 14.00 BSC 0.65 BSC MAX 0.50 2.90 NOTE 5 2 3 2 3 0.22 1.60 REF 0.40 4 3/29/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 100Q4, 100-lead, 14 x 20 mm Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 100Q4 REV. A 60 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA 144L1 - LQFP D1 D XX e E1 E CO U NT RY b Bottom View Top View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.05 1.35 1.40 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC 0.17 0.22 1.00 REF 0.27 4, 5 2, 3 2, 3 NOM MAX 0.15 1.45 NOTE 6 A2 A1 L1 A1 A2 D D1 E Side View E1 e b L1 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body. 11/30/01 REV. A R 2325 Orchard Parkway San Jose, CA 95131 TITLE 144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile Plastic Quad Flat Pack (LQFP) DRAWING NO. 144L1 61 0896C-FPGA-04/02 160Q1 - PQFP D1 D E1 E Top View A2 Bottom View A1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.25 3.20 NOM - 3.40 31.20 BSC 28.00 BSC 31.20 BSC 28.00 BSC 0.65 BSC 0.22 - 1.60 REF 0.40 4 MAX 0.50 3.60 2 3 2 3 NOTE 5 Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information. 2. To be determined at seating plane. 3. Regardless of the relative size of the upper and lower body sections, dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold Flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. Dimension b does not include Dambar protrusion. The Dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 5. A1 is defined as the distance from the seating plane to the lowest point of the package body. A1 A2 D D1 E E1 e b L1 3/28/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 160Q1 REV. A 62 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA 208Q1 - TQFP D1 A2 L1 E1 A1 Side View e b Top View D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A1 A2 MIN 0.25 3.20 3.40 30.60 BSC 28.00 BSC 30.60 BSC 28.00 BSC 0.50 BSC 0.17 1.30 REF 0.27 4 2, 3 2, 3 NOM MAX 0.50 3.60 NOTE E D D1 E E1 e b L1 Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 11/30/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.), Plastic Quad Flat Pack (PQFP) DRAWING NO. 208Q1 REV. A R 63 0896C-FPGA-04/02 240Q1 - PQFP D1 D E1 E Top View A2 Bottom View A1 e b L1 Side View SYMBOL A1 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation GA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. 3. To be determined at seating plane. 4. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Dimensions D1 and E1 shall be determined at datum plane. 5. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. The minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. A2 D D1 E E1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.25 3.20 NOM - 3.40 34.60 BSC 32.00 BSC 34.60 BSC 32.00 BSC 0.50 BSC 0.17 - 1.30 REF 0.27 5 MAX 0.50 3.60 3 2, 4 3 2, 4 NOTE 3/29/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 240Q1, 240-lead, 32 x 32 mm Body, 2.6 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 240Q1 REV. A 64 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 AT40K/AT40KLV Series FPGA 304Q1 - PQFP D D1 E1 E Top View A2 Bottom View A1 e b L1 Side View SYMBOL A1 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation JA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. 3. To be determined at seating plane. 4. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Dimensions D1 and E1 shall be determined at Datum plane. 5. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. The minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. A2 D D1 E E1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.25 3.55 NOM - 3.80 42.60 BSC 40.00 BSC 42.60 BSC 40.00 BSC 0.50 BSC 0.17 - 1.30 REF 0.27 5 MAX 0.50 4.05 3 2, 4 3 2, 4 NOTE 3/29/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 304Q1, 304-lead, 40 x 40 mm Body, 2.6 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 304Q1 REV. A 65 0896C-FPGA-04/02 352C1 - SBGA A1 BALL CORNER D 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A1 BALL CORNER b A1 BALL I.D. E e A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Top View Bottom View Die Side e A A2 A1 SEATING PLANE Section View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D E Matrix Size A - 0.35 0.25 0.60 MIN NOM 35.0 BSC 35.0 BSC 26 x 26 - - - 0.75 1.27 BSC 1.70 - 1.10 0.90 MAX NOTE Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-192, Variation BAR-2, for additional information. 2. JEDEC variations are based on fully populated ball arrays. Arrays can be depopulated as desired by removing balls from the fully populated array. A1 A2 b e 3/29/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 352C1, 352-ball, 35 x 35, Enhanced, Low-profile Square Ball Grid Array Package (SBGA) DRAWING NO. 352C1 REV. A 66 AT40K/AT40KLV Series FPGA 0896C-FPGA-04/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Programmable SLI Hotline (408) 436-4119 literature@atmel.com Atmel Programmable SLI e-mail fpga@atmel.com Web Site http://www.atmel.com FAQ Available on web site (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and Cache Logic (R) are the registered trademarks of Atmel. FreeRAM TM and QuickChange are the trademarks of Atmel. Concept(R), Verilog (R) and OrCAD (R) are the registered trademarks of Cadence Design Systems, Inc.; Mentor (R) and Veribest(R) are the registered trademarks of Mentor Graphics; Exemplar TM is the trademark of Mentor Graphics; SynarioTM is the trademark of Data I/O Corporation; Synopsys (R) is the registered trademark of Synopsis, Inc.; Viewlogic TM is the trademark of Viewlogic Systems, Inc.; Synplicity(R) is the registered trademark of Synplify, Inc. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0896C-FPGA-04/02 xM |
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